Rapid system prototyping with FPGAs / (Record no. 67204)

MARC details
000 -LEADER
fixed length control field 01505nam a2200337Ia 4500
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS
fixed length control field m u
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
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008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 050531s2006 ne a 001 0 eng d
010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
Canceled/invalid LC control number 2005015745
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 0750678666 pbk. : alk. paper
Qualifying information paperback
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 0080457371
Qualifying information paperback
024 3# - OTHER STANDARD IDENTIFIER
Canceled/invalid standard number or code 9780750678667
035 ## - SYSTEM CONTROL NUMBER
System control number (OCoLC)647549449
040 ## - CATALOGING SOURCE
Original cataloging agency CaPaEBR
Transcribing agency CaPaEBR
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Cofer, R. C.
245 10 - TITLE STATEMENT
Title Rapid system prototyping with FPGAs /
Statement of responsibility, etc. by R.C. Cofer and Benjamin F. Harding.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Amsterdam ;
-- Boston :
Name of publisher, distributor, etc. Elsevier/Newnes,
Date of publication, distribution, etc. c2006.
300 ## - PHYSICAL DESCRIPTION
Extent xv, 301 p. :
Other physical details ill.
490 1# - SERIES STATEMENT
Series statement Embedded technology series
500 ## - GENERAL NOTE
General note Includes index.
505 2# - FORMATTED CONTENTS NOTE
Formatted contents note FPGA fundamentals -- Optimizing the development cycle -- System engineering -- FPGA device-level design decisions -- Board-level design decisions & allocation -- Design implementation -- Design simulation -- Design constraints and optimization -- Configuration -- Board-level testing -- Advanced topics introduction -- Cores and intellectual property -- Embedded processing cores -- Digital signal processing -- Advanced interconnect -- Bringing it all together
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Digital electronics
General subdivision Computer-aided design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Field programmable gate arrays.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Rapid prototyping.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Harding, Benjamin F.
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Embedded technology series.
9 (RLIN) 41809
902 ## - LOCAL DATA ELEMENT B, LDB (RLIN)
a 170103
907 ## - LOCAL DATA ELEMENT G, LDG (RLIN)
a .b11118118
b m
c -
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Suppress in OPAC 0
998 ## - LOCAL CONTROL INFORMATION (RLIN)
Operator's initials, OID (RLIN) 1
Cataloger's initials, CIN (RLIN) 060329
First Date, FD (RLIN) m
Local a
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Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Shelving location Date acquired Cost, normal purchase price Full call number Barcode Date last seen Cost, replacement price Price effective from Koha item type
Not Withdrawn Not Lost Dewey Decimal Classification Not Damaged Available for Loan ATU Dublin Road ATU Dublin Road General Shelves 22/11/2005 41.61 621.381 COF J131919 05/04/2017 41.61 05/04/2017 General